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Espressif Systems /ESP32-S3 /RTC_CNTL /STATE0

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Interpret as STATE0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SW_CPU_INT)SW_CPU_INT 0 (SLP_REJECT_CAUSE_CLR)SLP_REJECT_CAUSE_CLR 0 (APB2RTC_BRIDGE_SEL)APB2RTC_BRIDGE_SEL 0 (SDIO_ACTIVE_IND)SDIO_ACTIVE_IND 0 (SLP_WAKEUP)SLP_WAKEUP 0 (SLP_REJECT)SLP_REJECT 0 (SLEEP_EN)SLEEP_EN

Description

configure chip sleep

Fields

SW_CPU_INT

rtc software interrupt to main cpu
SLP_REJECT_CAUSE_CLR

clear rtc sleep reject cause
APB2RTC_BRIDGE_SEL

1: APB to RTC using bridge, 0: APB to RTC using sync
SDIO_ACTIVE_IND

SDIO active indication
SLP_WAKEUP

leep wakeup bit
SLP_REJECT

leep reject bit
SLEEP_EN

sleep enable bit

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data